Design testbenches.
Not boilerplate.
We are a small team rethinking how Design Verification is done. DV Architect lets you drag, drop, and wire up your UVM hierarchy visually, generating robust SystemVerilog automatically.
Try Beta⚡ Unprecedented Speed
Drag an environment, drop in an agent, wire a scoreboard. Get a syntactically correct, fully connected UVM hierarchy in seconds.
👁️ Code2Visual Import
Import existing complex SystemVerilog environments. DV Architect parses your source files and instantly renders the full architectural hierarchy on the canvas.
�️ Compile-First Checks
The canvas prevents invalid UVM connections (like seq_item_port to an AP) before you even run your simulator.
🔄 Living Architecture
Your testbench diagram is no longer a static Visio file that goes out of date. It’s a living document synced with your actual codebase.
Free to Use
DV Architect is absolutely free to use. Download it, use it in your company, and speed up your workflow.
Where we are right now
DV Architect is just getting started. We've nailed the visual scaffolding, early code-generation, and vendor integrations (Verilator & Icarus). Our code parser is still maturing.
About Us
We are a small team of Design Verification engineers who got tired of writing the same UVM boilerplate over and over. DV Architect was born out of a need to bring the visual clarity of hardware design (like IP Integrators) into the verification world. We believe DV engineers should spend their time finding bugs, not debugging typos in their connect_phase.
Join Us: We are looking for talented engineers who want to join us and build the future of visual EDA tools. If you are passionate about redefining verification workflows, we'd love to hear from you!